Fetch Decode Execute Cycle. Registers. System bus. Addressing mode.

The control unit coordinates and controls all the operations carried out by the computer. It operates by repeating three operations:

Fetch - the CPU fetches some data and instructions from the main memory (RAM) and then store them in its own temporary memory called 'registers';

Decode - is where the CPU understands/works out what the instruction it has just fetched actually means. 
The CPU ‘decodes’ the instruction and gets things ready for the next step;

Execute - is where data processing happens. Instructions are carried out on the data. 

When once a cycle has been completed, a new cycle begins.

Program Counter (PC) - an incrementing counter that keeps track of the memory address of which instruction is to be executed next.

Memory Address Register (MAR) - the address in main memory that is currently being read or written.

Memory Buffer Register (MBR) or Memory Data Register (MDR) - a two-way register that holds data fetched from memory (and ready for the CPU to process) or data waiting to be stored in memory.

Current Instruction register (CIR) - a temporary holding ground for the instruction that has just been fetched from memory.

Accumulator (ACC) - an internal CPU register used as the default location to store any calculations performed by the arithmetic and logic unit.

Control Unit (CU) - decodes the program instruction in the CIR, selecting machine resources such as a data source register and a particular arithmetic operation, and coordinates the activation of those resources.

Arithmetic logic unit (ALU) - performs mathematical and logical operations.

MAR <== [PC]

MBR <== MAR; PC <== [PC]+1

CIR <== [MBR]

[CIR] executes

System bus is the main highway (a set of parallel wires) connecting the processor, main memory and I/O controllers. The processor is connected to the main memory by three separate buses. When the CPU wishes to access a particular main memory location, it sends this address to memory on the address bus. The data in that location is then returned to the CPU on the data bus. Control signals are sent along the control bus.


Control bus (bi-directional) The purpose of the control bus is to transmit command, timing, and specific status information between system components.

Data bus a bi-directional path for moving data and instructions between system components. The width of the data bus is a key factor in determining overall system performance. For example, if the data bus is 16 bits wide, and each instruction is 32 bits long, then the processor must access the main memory twice just to fetch the instruction.

Address bus used to specify a physical address in memory so that the data bus can access it. 1directional

The width of the address bus determines the maximum possible memory capacity of the system.

For example, if the address bus consisted of only 8 lines, then the maximum address it could transmit would be 255 or 11111111 (in binary), giving a maximum memory capacity of 256 (including address 0). A system with a 32-bit address bus can address 232 (4 294 967 296) memory locations giving an addressable memory space of 4Gb.

I/O Controllers a device that interfaces between an input or output device and the processor.

An interface is a standardized form of connection defining such things as signals, the number of connecting pins/sockets, and voltage levels that appear at the interface.

Clock speed - the number of cycles that are performed by the CPU per second.

Word length - the number of bits of information that the CPU can process at a time.

Bus width - the number of bits of information a bus can carry at one time.


The addressing mode defines the rule for interpreting or modifying the address field of an instruction before actually executing the operand.

In immediate addressing, the operand is the actual value to be operated on, say 3 or 75.

Example, LDA #12 means load the number 12 into the accumulator

In direct addressing, the operand holds the memory address of the value to be operated on.

Example, LDA 103 means load the number to the accumulator from location 103

Indirect addressing means that the address of the data is held in an intermediate location so that the address is first ‘looked up’ and then used to locate the data itself. 

Indexed addressing means that the final address for the data is determined by adding an offset to a base address.


CISC Complex Instruction Set

RISC Reduced Instruction Set

Non-fixed size of instruction, e.g. instructions have variable format.

Fixed-size of instruction

Uses complex instructions each of which may take multiple cycles.

Complex tasks can only be performed by combining several simple tasks so a task may take several machine cycles.

Many instructions and addressing modes are available. Can perform complex tasks faster.

A limited number of instructions are available. The instruction performs a simple task. Can perform simple tasks faster.

Small code sizes

Large code sizes

High cycles per second

Low cycles per second

Has a complicated and expensive processor design.

Simple processor design.

Has more components on the CPU than a RISC processor

Less components on CPU than in CISC processor

Use less RAM 

Use more RAM

Produces more heat, requires heat sink/fan

Produces less heat

Used in PC

Used in tablets and mobile devices

Memory-to-memory

Register-to-register

Require more power

Require less power

Uses less registers than in RISC

Uses more registers than in CISC



Последнее изменение: Tuesday, 16 April 2024, 14:52